| Peer-Reviewed

The Design of Three Phase Programmable Testing Power Based on CPLD_DSP

Received: 3 August 2019     Accepted: 19 August 2019     Published: 3 September 2019
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Abstract

A design of three phases programmable testing power program-controlled based on CPLD_DSP was introduced in the paper. RAM was driven and six DDS were generated in CPLD. RAM was driven and six DDS (three voltage signal and three current signal) were generated in CPLD. The six DDS signal was used as based signal of testing power. CPLD was programmed to control serial D/A chip named LTC1595B to adjust the value of voltage and current. Voltage signal and current signal were collected and computed and closed loop by DSP. After testing, the output frequency resolution of the system achieved 0.001Hz.The voltage and current control precision achieved 0.02%.

Published in Advances in Wireless Communications and Networks (Volume 5, Issue 1)
DOI 10.11648/j.awcn.20190501.12
Page(s) 13-18
Creative Commons

This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited.

Copyright

Copyright © The Author(s), 2019. Published by Science Publishing Group

Keywords

Testing Power, CPLD, DDS, Output Precision

References
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[6] Liu Jiang Hai. EDA technology [M]. Wuhan: Huazhong University of Science and Technology Press, 2013.
[7] HAN Xu,YU Xiao-yi. Design of DDS Signal Generator Based on PSOC [J]. Electrical Measurement & Instrumentation, 2012, 49, (03): 85-88.
[8] LI Xue-mei, ZHANG Hong-cai, WANG Xue-wei. The Design of a Signal Source Based on DDS Technology [J]. Electrical Measurement & Instrumentation, 2010, 47 (01): 55-66.
[9] Li wen bing, Hao qiang, Du yuan bo, et al. Demonstration of a Sub-Sampling Phase Lock Loop Based Microwave Source for Reducing Dick Effect in Atomic Clocks [J]. Chinese Physics Letters, 2019, 36 (07): 23-26.
[10] WANG Hong-liang, HUANG Yang-wen. Design of Programmable Multi-signal Generator based on FPGA [J]. Fire Control & Command Control, 2010, 35, (06): 97-99.
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Cite This Article
  • APA Style

    Li Hui, Li Jing. (2019). The Design of Three Phase Programmable Testing Power Based on CPLD_DSP. Advances in Wireless Communications and Networks, 5(1), 13-18. https://doi.org/10.11648/j.awcn.20190501.12

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    ACS Style

    Li Hui; Li Jing. The Design of Three Phase Programmable Testing Power Based on CPLD_DSP. Adv. Wirel. Commun. Netw. 2019, 5(1), 13-18. doi: 10.11648/j.awcn.20190501.12

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    AMA Style

    Li Hui, Li Jing. The Design of Three Phase Programmable Testing Power Based on CPLD_DSP. Adv Wirel Commun Netw. 2019;5(1):13-18. doi: 10.11648/j.awcn.20190501.12

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  • @article{10.11648/j.awcn.20190501.12,
      author = {Li Hui and Li Jing},
      title = {The Design of Three Phase Programmable Testing Power Based on CPLD_DSP},
      journal = {Advances in Wireless Communications and Networks},
      volume = {5},
      number = {1},
      pages = {13-18},
      doi = {10.11648/j.awcn.20190501.12},
      url = {https://doi.org/10.11648/j.awcn.20190501.12},
      eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.awcn.20190501.12},
      abstract = {A design of three phases programmable testing power program-controlled based on CPLD_DSP was introduced in the paper. RAM was driven and six DDS were generated in CPLD. RAM was driven and six DDS (three voltage signal and three current signal) were generated in CPLD. The six DDS signal was used as based signal of testing power. CPLD was programmed to control serial D/A chip named LTC1595B to adjust the value of voltage and current. Voltage signal and current signal were collected and computed and closed loop by DSP. After testing, the output frequency resolution of the system achieved 0.001Hz.The voltage and current control precision achieved 0.02%.},
     year = {2019}
    }
    

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    T1  - The Design of Three Phase Programmable Testing Power Based on CPLD_DSP
    AU  - Li Hui
    AU  - Li Jing
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    JF  - Advances in Wireless Communications and Networks
    JO  - Advances in Wireless Communications and Networks
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    AB  - A design of three phases programmable testing power program-controlled based on CPLD_DSP was introduced in the paper. RAM was driven and six DDS were generated in CPLD. RAM was driven and six DDS (three voltage signal and three current signal) were generated in CPLD. The six DDS signal was used as based signal of testing power. CPLD was programmed to control serial D/A chip named LTC1595B to adjust the value of voltage and current. Voltage signal and current signal were collected and computed and closed loop by DSP. After testing, the output frequency resolution of the system achieved 0.001Hz.The voltage and current control precision achieved 0.02%.
    VL  - 5
    IS  - 1
    ER  - 

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Author Information
  • Automated Institute, Huaiyin Institute of Technology, Huaian, China

  • Automated Institute, Huaiyin Institute of Technology, Huaian, China

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